This invention is related generally a method of making a semiconductor device and specifically to a dual damascene process using a bilayer resist.
In order to increase the miniaturization of semiconductor devices, contacts between conductive layers in a semiconductor device are formed by the dual damascene process which utilizes a dual inlaid via. It has recently been suggested in the article titled xe2x80x9cDUAL DAMASCENE: OVERCOMING PROCESS ISSUESxe2x80x9d by Ruth DeJule in the June 2000 issue of SEMICONDUCTOR INTERNATIONAL to use a bilayer resist to form a dual inlaid via for a dual damascene process. An example of the xe2x80x9cvia first xe2x80x9d dual damascene process using a bilayer resist, similar to the one described in the DeJule article, is illustrated in FIGS. 1A-F.
FIG. 1A illustrates a portion of an in process metallization section 1 of a semiconductor device. The metallization section contains a first conductive layer 3 and an insulating layer 5 formed over the first conductive layer 3. The conductive layer 3 may be a metal interconnect, such as an aluminum interconnect. The insulating layer 5 contains a narrow via 7 which extends from the top surface 9 of the insulating layer 7 to the first conductive layer 3. The via 7 has a circular cross section and contains only one sidewall 11 having a circular perimeter.
A conventional, bilayer resist film 12, is formed in the via 7 and over the upper surface 9 of the insulating layer 5, as shown in FIG. 1B. The bilayer resist 12 includes a bottom antireflection coating (xe2x80x9cBARCxe2x80x9d) 13 and a top imaging layer 14. The BARC 13 is typically a water soluble organic fluoropolymer which absorbs rather than reflects a majority of the exposing radiation. The top imaging layer 14 is a silicon containing polymer, such as a silane polymer, that is sensitive to selective radiation exposure. As shown in FIG. 1B, the bilayer resist 12 has a thickness of 2,500 to 3,500 angstroms. However, the BARC 13 is relatively thin and does not extend far above the upper surface 9 of the insulating layer. For example, the BARC 13 extends less than about 100 angstroms above the upper surface 9 of the insulating layer, creating a dip or recess 10 above the via 7. A small portion of the imaging layer 14 is present in the recess 10 in the BARC 13 above the top portion of the via 7.
The bilayer resist 12 is selectively exposed to radiation through a conventional lithographic mask or reticule (not shown), as illustrated in FIG. 1C. During the exposure, a first portion 15 of the imaging layer 14 over the upper surface 9 of the insulating layer 5 directly adjacent to via 7 sidewall 11 and a second portion 17 of the imaging layer 14 above the via 7 are exposed, as indicated by the cross hatching in FIG. 1C. A third portion 19 of the imaging layer 14 over the upper surface 9 of the insulating layer 5 distal from the via sidewall 11, is shielded by the mask and is not exposed to radiation. The exposed positive imaging layer 14 is then developed and patterned to remove the exposed first and second portions 15, 17 while leaving the third portion 19 of the imaging layer 14 on the BARC 13 as a mask.
The exposed first portion 15A of the BARC 13 above the upper surface of the insulating layer 5 and a second portion 17A of the BARC 13 in the via 7 are removed by selective etching, such as by oxygen plasma etching, as illustrated in FIG. 1D. The third portion 19A of the BARC 13 that is masked by the third portion 19 of the imaging layer 14 is not removed because the imaging layer is not substantially removed by the oxygen plasma. The removal of the first and second portions 15A, 17A of the BARC 13 exposes a portion of upper surface 9 of the insulating layer 5.
The exposed portion of the insulating layer 5 is etched using the third portion 19/19A of the bilayer resist 12 as a mask to form a trench 21 having a width greater than that of the via 7. The remaining third portion 19/19A of the bilayer resist 12 is then removed by conventional methods, as illustrated in FIG. 1E. The top of the via 7 is located in a bottom surface 23 of the trench 21. In other words, the exposed portion of the insulating layer 5 is etched to remove a top section of the exposed portion of the insulating layer, without etching the bottom section of the exposed portion.
The dual damascene process is then completed by forming a second conductive layer 25, as illustrated in FIG. 1F. The second conductive layer 25 may be a metal layer which is formed in the trench 21, such that it extends through the via 7 to contact the first conductive layer 3. The second conductive layer is planarized by chemical mechanical polishing or etch back such that its top surface is even with the upper surface 9 of the insulating layer 5.
However, the prior art dual damascene process suffers from a problem of via poisoning. This problem is illustrated in FIG. 2. During the bilayer resist 12 exposure step illustrated in FIG. 1C, the second portion 17A of the BARC 13 binds to the via 7 sidewall 11 and forms a rigid mushroom shape, as shown in FIG. 2. The bound top section of the second portion 17A is schematically illustrated by double cross hatches. Therefore, the second portion 17A of the BARC 13 cannot be removed or fully removed from the via 7 during subsequent oxygen plasma etching step because it is chemically and/or physically bound to the via sidewall 11. Thus, the second conductive layer 25 cannot contact or fully contact the first conductive layer 3 through the via 7, because the via 7 is filled by the second portion 17A of the BARC 13 which is rigidly bound to the via 7 sidewall 11. This causes an open circuit between the first and second conductive layers or a poorly conductive path there between, which leads to device failure. This poison via problem is especially severe when the insulating layer 5 is a low-k (i.e., a low dielectric constant) polymer material, such as hydrogensilsesquioxane (HSQ).
According to one aspect of the present invention, there is provided a method of making a dual inlaid via in a first layer, comprising forming a first opening in the first layer, forming a bilayer resist comprising an imaging layer above a BARC in the first opening, such that a lower section of the BARC is located in the first opening and an upper section of the BARC extends above the first opening, selectively exposing the imaging layer to radiation, patterning the bilayer resist, forming a second opening in communication with the first opening using the patterned bilayer resist as a mask, and wherein said bilayer resist forming step includes forming the BARC such that said upper section of the BARC extends above the first opening to a first height that is sufficient to substantially prevent exposing radiation from reaching a lower section of the BARC located in the first opening.
According to another aspect of the present invention, there is provided a method of making a semiconductor device containing a dual damascene contact, comprising forming a via in a polymer containing insulating layer, forming a bilayer resist comprising an imaging layer above a BARC in the via, such that a lower section of the BARC is located in said via and an upper section of the BARC extends above the via, selectively exposing the imaging layer to radiation and patterning the exposed imaging layer to remove a first portion of the imaging layer above the upper surface of the insulating layer adjacent to via sidewall and a second portion of the imaging layer over the via, while leaving a third portion of the imaging layer over the upper surface of the insulating layer distal from the via sidewall. The method further comprises removing a first portion of the BARC above the upper surface of the insulating layer adjacent to the via sidewall and a second portion of the BARC in the via, while leaving a third portion of the BARC that is masked by the third portion of the imaging layer on the upper surface of the insulating layer distal from the via sidewall and etching an exposed upper portion of the insulating layer using the third portion of the imaging layer and the third portion of the BARC as a mask to form a trench having a width greater than that of the via, such that a top of the via is located in a bottom surface of the trench. The bilayer resist forming step includes forming the BARC such that said upper section of the BARC extends above the via to a first height that is sufficient to substantially prevent exposing radiation from reaching a lower section of the BARC located in the via
According to another aspect of the present invention, there is provided a method of making a semiconductor device containing a dual damascene contact, comprising forming an active element over a substrate, forming a first conductive layer over the active element, forming an insulating layer comprising hydrogensilsesquioxane over the first conductive layer and forming a first resist over the insulating layer. The method further comprises selectively exposing the first resist to radiation, patterning the first resist, etching the insulating layer using the patterned first resist as a mask to form a via extending through the insulating layer to the first conductive layer and removing the first resist. The method further comprises forming a bilayer resist comprising an imaging layer above a BARC in the via, such that a lower section of the BARC is located in said via and an upper section of the BARC extends above the via, selectively exposing the imaging layer to radiation and patterning the exposed imaging layer to remove a first portion of the imaging layer above the upper surface of the insulating layer adjacent to via sidewall and a second portion of the imaging layer over the via, while leaving a third portion of the imaging layer on the BARC over the upper surface of the insulating layer distal from the via sidewall. The method further comprises removing a first portion of the BARC above the upper surface of the insulating layer adjacent to the via sidewall and a second portion of the BARC in the via, while leaving a third portion of the BARC that is masked by the third portion of the imaging layer on the upper surface of the insulating layer distal from the via sidewall and etching an exposed upper portion of the insulating layer using the third portion of the imaging layer and the third portion of the BARC as a mask to form a trench having a width greater than that of the via, such that a top of the via is located in a bottom surface of the trench. The method further comprises forming a second conductive layer in the trench such that the second conductive layer contacts the first conductive layer through the via and planarizing the second conductive layer such that a top surface of the second conductive layer is substantially level with the upper surface of the insulating layer. The bilayer resist forming step includes forming the BARC such that said upper section of the BARC extends above the via to a first height that is sufficient to substantially prevent exposing radiation from reaching a lower section of the BARC located in the via.